today at 6:21 AM
> Engineering sample silicon for Agilex 27 FPGAs is expected in the second half of 2027.
That's not even a paper launch at this stage.
today at 9:14 AM
quite typical with FPGAs. Plus this is the general public announcement. Key customers likely already have samples since a while
today at 10:36 AM
I would have expected that Engineering samples would be already available or soon, not in one year or more.
today at 9:49 AM
Can anyone comment on Altera since they have escaped from Intel ? And how it fares again Xilinx / AMD?
My old perception was still based on pre AMD Xilinx era from 4-5 years ago and Xilinx was basically winning 60-70% market shares as Intel Altera was no where near competitive. ( As usual with any Intel acquisition)
today at 11:03 AM
I worked there for 3 years, and still catch up with everyone from time to time at tradeshows and the occasional social. They definitely seem in much better spirits, but I'll be brutally honest, many of the people I knew that were the top talent have moved to AMD or Lattice. It's a lot of new faces last time I was there, from a mix of different companies (ADI, TI, Microchip, etc), so I guess time will tell whether some fresh bodies do something interesting.
They restricted wage growth too much for too long under Intel (despite being the only growing business unit), so the people with the valuable experience moved elsewhere. The Agilex line-up finally looks to be in the place it should have been 3 years ago, and it seems like they brought in a good marketing team following the Silverlake acquisition, but they still fall in this weird middle-ground now selling "performance-per-watt", which is a hard sell when most engineers optimise for the extremes. If I'm just need a bridge or some glue-logic, I don't need a device which will singe my thumbprints off while doing that. Generally, if you want better performance, AMD does an excellent job, or if you need low power consumption, Lattice is like 4 or 5x lower or more with just enough fmax and IO to be dangerous. If you look read Lattice's shareholder briefings, they're running away with the low/mid-range devices up to ~500k LUTs, and AMD is dominating anything 1M+. I couldn't help but laugh the other day when I saw an Intel reference design with a Lattice MachXO5-NX on it. Look at pretty much any datacentre rack now, and you'll spot 4-64 Lattice devices, when it used to be MAX10s top to bottom. Everything else is swept up by AMD.
For Altera, Agilex 9 (ADC and DAC converters integrated with an SoC FPGA) is probably their most interesting device, but that customer base is limited - basically comms and maybe radar with some weird and wonderful optical or quantum compute applications. I've heard friends of mine in the industry say very good things about it, but RF is not my strength so I can't comment.
In all honesty, they've got an insane fight on their hands to regain the market share. They canned their low end road-map when Sandra Riviera came in (as a classic Intel VP would do) and put all their eggs in the Agilex 7 basket for a long time. They've got Agilex 5 now (and Agilex 3, which is just the bottom SKUs of 5 with it painted over by marketing to fill the gap), which is great for vision applications, but only because they had a fantastic video and vision IP team who last I heard have left for ARM.
I hope they pull it back, as I loved the people there and it had a great culture, but it's been awfully mismanaged for a while and I question how easy it will be to pull it back considering the monopolies and duopolies that are appearing in the semi industry right now.
today at 8:06 AM
Hopefully the hard NOC is good this time around. The limitations of the previous series made it mostly useless.
today at 6:59 AM
Likely shipping w/o the proper documentation to enable nextpnr and similar tools, as it's tradition in altera.
I will always choose the vendors that do things properly, when they're even an option.
today at 7:14 AM
Like which ones? Honest question.
today at 7:59 AM
There aren't any open commercial FPGAs as far as I know. Some have had their bitstream formats reverse engineered though.
We're starting to see open source FPGAs but they are miniscule: https://tinytapeout.com/chips/ttihp26a/tt_um_fabulous_ihp_26...
today at 8:40 AM
I think Efinix did something internally, with Yosys.
today at 7:57 AM
Not many options unfortunately. Today that's GateMate.
Next best thing? The mature reverse-engineered families nextpnr[0] supports.
0. https://github.com/YosysHQ/nextpnrhttps://github.com/YosysHQ...
today at 8:25 AM
> Not many options unfortunately. Today that's GateMate.
And that's not a great option, frankly. GateMate is a strange design with major performance issues, like the lack of a dedicated clock network.
today at 7:46 AM
[flagged]
today at 7:44 AM
Fantastic chip, I love everything about this announcement.