> The fix is to set bit 13 of MCSR24 to 1. MCSR24 is an internal CSR whose function is not described in the manual. After setting this bit, the lost update no longer occurs. Testing showed the performance loss is very small: single-core performance is unaffected, and multi-core performance drops only slightly.

Presumably this is a so-called “chicken bit”.

• aleph_minus_one

  today at 6:55 PM

  > Presumably this is a so-called “chicken bit”.

  For those who are out of the loop:

  > https://lwn.net/Articles/744840/

  See also

  > https://en.wiktionary.org/wiki/chicken_bit

  (click on "quotations") for a list of scientific texts in which this term occurs.

  • jacquesm

    today at 9:47 PM

    Famously, the first GPS satellites had one of these, in case Einstein was wrong...

    https://www.quora.com/Why-did-the-GPS-system-initially-resis...

    He wasn't.

  • oynqr

    today at 7:52 PM

    more like out of the coop

• monocasa

  today at 6:48 PM

  Pretty much the definition of.

  Some optimization that turned out to be buggy had a disable bit in an undocumented register.

• today at 6:48 PM