\

Rust SIMD on the GPU

169 points - yesterday at 6:12 PM

Source
  • O3marchnative

    yesterday at 8:37 PM

    The author mentions Rust's portable SIMD library [0]. The only issue with portable SIMD is it's only available on nightly. I used it in my FFT crate, but we had to switch to the fearless_simd crate in order to get a portable SIMD solution that works on stable [1].

    [0] https://doc.rust-lang.org/std/simd/index.html

    [1] https://github.com/linebender/fearless_simd

      • jonkoops

        yesterday at 10:02 PM

        Pretty common for Rust to cook things in nightly for a very long time; I wouldn't consider it a bad thing, tbh.

          • LoganDark

            today at 3:48 AM

            It's been annoying to me as an end user that so many basic things require nightly. I use nightly as my main toolchain, but enabling unstable features makes a project nightly-only, which is undesired for crates that don't already revolve around the unstable feature.

            I most often encounter unstable features when I reach for a basic common-sense utility method and discover that it's not stable. Like just earlier today I would have reached for bool::toggle which not only is unstable, but is also newly added as of like a month ago! but some unstable methods have been sitting around for years.

            And now that IntelliJ-Rust is proprietary, I can't even make a feature request anymore for the ability to exclude unstable features from the autocomplete. So they will taunt me forever, perfect little helpers just locked away.

              • nirvdrum

                today at 5:43 AM

                [dead]

    • 6r17

      yesterday at 8:00 PM

      My heard hurts - i was stupid enough to think that SIMD was a CPU only thing - I don't understand why it would be ported to GPU - huge kudos to managing to surprise me

        • MindSpunk

          today at 2:10 AM

          It's not really obvious unless you go in depth of the details on modern GPU architecture. GPUs aren't really SIMD, they're SIMT (single instruction multiple thread). The silicon looks a lot like SIMD, but the programming model is different.

          If you go look at AMD's ISA docs (they're public) you'll see you don't have the equivalent of a __mm256 register like on x86. Each 'thread' just deals with single scalar values like int32 of float32. The hardware, however, groups 32 or 64 threads together which all run the same program and runs them together. Each 'thread' loosely maps to a SIMD lane. The SIMD is implicit, not explicit.

          The main difference is that the 'SIMD' execution is somewhat opaque to the program. You just write plain scalar code and the hardware model dispatches it efficiently to SIMD execution units. It's not really an abstraction because to extract maximum performance you have to understand how it works. You can use this kind of programming model on a CPU too, Intel did it with [0] ISPC. It's a C-like language that has execution semantics similar to GPU shader languages but compiles to regular CPU code, and maps threads to your CPUs SIMD lanes like a GPU.

          [0] https://ispc.github.io/

            • mathisfun123

              today at 4:42 AM

              > GPUs aren't really SIMD, they're SIMT (single instruction multiple thread)

              False. If they were threads they'd have their own PC. They do not - only the warp has a PC.

              > You just write plain scalar code and the hardware model dispatches it efficiently to SIMD execution units.

              Absolutely not. If you don't write coalesced loads, bank-conflict free, predication-free, cooperative code you will get worse than CPU performance.

                • MindSpunk

                  today at 5:21 AM

                  Yes, of course writing naive code assuming each lane in a thread group is a real thread is going to cause problems, but I didn't feel like I needed to go into that level of detail replying to someone just learning about GPU internals. I tried to cover this loosely by mentioning how you need to know how it works for maximum performance.

                  If you want to get more pedantic you also need to look at your target hardware and their specific micro-architectural quirks and features to get the best performance. AMD specifically benefits a lot from exploiting the scalar unit over the vector unit, you save loads of register file space if you can keep data in SGPRs over VGPRs. There's lots of traps you can fall into where you can load data from buffers into SGPRs but they get promoted to VGPRs because the scalar unit lacks an opcode for like one math operation you did to the value somewhere.

                  While each lane isn't truly a thread because it doesn't have its own PC the programming model definitely tries to make it seem that way. The threads can terminate at different points too. And again, the ISA isn't a vector ISA. Your register values are scalar.

          • monocasa

            yesterday at 9:39 PM

            GPU "cores" are basically what a CPU would call SIMD lanes. So a GPU with 1024 'CUDA cores' might be structured as 16 relatively independent pieces that a CPU might call a core, each with a 64 wide SIMD unit.

              • y1n0

                today at 12:47 AM

                64 what? Bits/bytes/something bigger?

                  • corysama

                    today at 1:08 AM

                    When you dig through the CUDA developer docs instead of the promotional materials, you can develop a view of Nvidia GPUs as having 8-128 processing cores, each with 4 hyperthreads, running 32-lane SIMD for almost everything. Where a lane is 32 bits wide.

                    The promotional material likes to label the individual lanes as “cores” because it sounds more impressive. And, it’s not entirely incorrect.

                    Even the dev docs use the marketing terminology. The description I gave above needs a bit of piecing together.

                      • dataflow

                        today at 4:33 AM

                        This is a fantastic explanation, thanks for writing it. It also makes me wonder something: where exactly is the biggest difference between a 32-core x86 CPU (AVX512 basically being 16 32-bit lanes) and (say) an NVIDIA GPU with ~8-16 processing cores? Like why can't the CPU compete against a GPU like that for GPU-y tasks - or can it?

                          • jandrewrogers

                            today at 5:29 AM

                            At risk of over-simplifying, GPUs are wider with limited computational expressiveness and higher memory bandwidth while CPUs are highly expressive computationally (and better connected to I/O) but with lower memory bandwidth. GPUs are less sensitive to memory latency by necessity. Even AVX-512 is highly flexible when inter-mixed with scalar code. GPUs get their very high register width by restricting what the cores are capable of doing efficiently.

                            Current CPU cores do two AVX-512 operations per cycle. If you can saturate this you’ll often run out of memory bandwidth on CPUs because of lower bandwidth compared to GPUs. In principle, if you bought a 192-core processor you’d have 6,144 GPU-ish cores of 32-bit operations, and they would run at a significantly higher clock rate than a GPU. It would not be competitive with a GPU for the kinds of things GPUs are good at it but it wouldn’t be as far off as you might assume. For some types of code, AVX-512 is unambiguously better.

                            Horses for courses. GPUs and CPUs were optimized for different things but their capabilities have slowly been converging over time. They all work from the same transistor budgets, the differences are where the tradeoffs are made.

                            There is a pithy silicon architecture tradeoff trilemma to be made regarding CPUs, GPUs, and barrel processors.

                            • monocasa

                              today at 5:02 AM

                              Not corysama, but I'll take a stab:

                              The major one is that there's one layer of indirection that exists on GPUs that doesn't really on CPUs. There's one giant vector register file per for each of these processing cores (that'll be something like 2048 rows x 32 lanes x 32 bits). An individual shader invocation might only need say, 16 rows. While there's hardware for issuing 4 hyperthreads at any given time, there can be a variable number of thread states in the register file. So for the case of each invocation only needing 16 rows, you might be able to fit 128 hyperthread states into processing core. Those four hyperthreads then hardware schedule those 128 states and will execute any that are ready, as well as allocate more from other scheduling hardware as gaps in the register file appear from shaders completing.

                              Because of this massive amount thread state, you don't depend nearly as much on a cache hierarchy to deal with DRAM latency. There's ostensibly some other thread state sitting around that can be serviced while others wait for the hundreds of cycles of latency to access DRAM.

                              So the whole model of how you account for the discrepancy between ALU cycle time, and DRAM latency changes versus a CPU. Where a modern CPU spends a lot of area on complex cache hierarchies, speculation, etc, to hide the latency to memory, a GPU focuses on having a lot of thread state around and a lot of ALUs, but balanced ideally, so there's always ALU work to do while other thread states are waiting on memory.

                              Now, over time, GPUs have gotten more complex hardware, and more complex cache hierarchies to cover the cases that aren't handled well by extremely long access times. But those tend to be very explicit. Additionally, CPU vector files have gotten more similar to GPU cores as architectural features like lane masking/predicates have been added to have the equivalent of CUDA threads in the same warp that take different paths through control flow blocks. That's a lot of what people mean when they say that AVX-512 adds a lot more than just 512-bit registers. The K mask registers let you do a lot of GPU shader tricks to have effective partial residency, and not have to use all the lanes if the data doesn't line up with that.

                              • dahart

                                today at 5:31 AM

                                If by processing cores you mean Streaming Multiprocessors (SMs), keep in mind that each SM is 128 threads, so 16 SMs is 2k threads - or 2048 single precision math ops per cycle. The 32 core avx512-enabled CPU is 512 math ops per cycle, if you have one FMA unit per core (or 1k ops/cycle if you have 2 FMA units/core).

                                Note that modern NVIDA GPUs like the 5090 are actually more like 170 SMs on a chip, or 21,760 flop/cycle, or ~20-40x more ops/cycle than your example CPU.

                                Put GDDR6 vs DDR5 memory on top of that, and it’s easy to see why the GPU can churn through math so fast … as long as it’s GPU-y. For stuff the GPU does well, the CPU typically can’t compete, the GPU is often more than 10x faster. But GPU-y tasks are a subset, and there are CPU-y things the GPU can’t compete on, despite (or even because of) the thread count discrepancy.

                    • mathisfun123

                      yesterday at 10:04 PM

                      32 wide - only AMD has a 64 wide mode

                  • chlorion

                    yesterday at 8:23 PM

                    GPUs work on vectors and matrices very often, that's what they are good at, so it makes a lot of sense that they can operate with SIMD I think!

                    • ismailmaj

                      yesterday at 9:11 PM

                      There is something very SIMD-coded in GPU programming which is coalesced stores/loads, if a warp (32 threads) handles contiguous memory, it will create ~4 transactions instead of 32.

                      • hingler36

                        yesterday at 8:08 PM

                        Welcome to the lucky 10,000! SIMD is actually a pretty integral part of how GPUs are able to work efficiently, it's part of why there's such a strong focus on branchless programming in the field.

                    • camel-cdr

                      yesterday at 9:11 PM

                      I love how ever example of portable SIMD isn't portable.

                      They specifies a constant SIMD width so it's non-portable. Well, not performance portable, but why are we using SIMD again?

                        • exDM69

                          today at 7:08 AM

                          > They specifies a constant SIMD width so it's non-portable.

                          This is incorrect, you can use vectors wider than native SIMD width and the compiler will break them down to register size of the target cpu.

                          In fact it's sometimes better to used wider than native width, I see 20% better throughput with f32x16 (512 bits) on an AVX2 CPU (256 bits). It is kinda like loop unrolling it.

                          • jandrewrogers

                            today at 2:19 AM

                            The capabilities of various SIMD ISAs don't have enough intersection to be portable outside of relatively trivial cases. Many of the somewhat unique capabilities are load-bearing, so you want to use them on architectures that support them. Taken in whole, someone who cares about performance would be using different data structures and algorithms depending on the specific SIMD architecture and that is nearly impossible to abstract in a library. Too many important but complex details are idiosyncratic to the implementation.

                            Another way of looking at it is that our programming environments are not sufficiently powerful and expressive to create the necessary abstractions to make SIMD truly portable.

                            • zamadatix

                              yesterday at 10:52 PM

                              It should really be read/advertised as "portabler SIMD". It beats hoping the compiler autovectorizes everything well forever or writing architecture specific code manually again but is going to compromise on average performance vs platform specific SIMD.

                                • pjmlp

                                  today at 6:22 AM

                                  .NET and Java have three levels of SIMD support, Go's ongoing efforts, and does the upcoming C++ standard.

                                  Autovectorization, depending on compiler's cleverness, really portable SIMD operations, and then the CPU specific SIMD ones.

                                  So this should be perfectly doable in crate that advertises as portable, while leaving the non portable stuff to another crate.

                              • tyho

                                yesterday at 9:36 PM

                                Go's implementation is vector size independant https://pkg.go.dev/simd@master

                                  • IshKebab

                                    yesterday at 11:10 PM

                                    Sure but there's no real way to use that in a portable way, at least not a way that maximises performance on every CPU you run it on. That's pretty much impossible at the moment.

                                      • krapht

                                        yesterday at 11:47 PM

                                        Which is why I've never quite understood the appeal of portable SIMD libraries for performance-critical code. If I'm explicitly writing SIMD rather than relying on the auto-vectorizer, it's usually because I want access to the particular capabilities of the target ISA.

                                        For many problems, choosing the right instruction or instruction sequence makes a large difference. Portable SIMD abstractions necessarily expose some common semantic layer, but SIMD ISAs don't actually have equivalent capabilities. Instructions like pshufb, for example, enable algorithmic tricks that don't necessarily have an equally efficient analogue on another architecture.

                                        If maximum performance matters, I generally want intrinsics and architecture-specific implementations; if portability matters more, I'd rather move further up the abstraction stack and use something designed to target multiple architectures, such as ISPC. There are certainly cases where portable SIMD gets close enough to optimal, but I don't think there's a compiler or abstraction that can express every useful SIMD idiom and lower it equally efficiently across fundamentally different ISAs.

                                          • pjmlp

                                            today at 6:25 AM

                                            Because usually they achieve a very good middle ground, they are useful for when autovectorization isn't good enough, and it is possible to give a little help to the compiler.

                                            There are many ways that performance matters without trying to win a F1 race.

                                            Go isn't alone, .NET, Java have similar portable libraries, and C++ is in the process of getting one.

                                • MomsAVoxell

                                  yesterday at 10:09 PM

                                  Why should it be portable? Honest question.

                                  SIMD seems to me, to be very platform specific. Maybe there are times one SIMD unit is not anothers' SIMD unit?

                                    • camel-cdr

                                      yesterday at 10:14 PM

                                      The create is called portable_simd.

                                      There is no reason a portable_simd relu_dot implemention should need to specify the SIMD width.

                                      But the design and documentation of portable_simd makes the fixed size syntactically easy/the default and the width agnostic code harder.

                                        • dwattttt

                                          yesterday at 11:17 PM

                                          > There is no reason a portable_simd relu_dot implemention should need to specify the SIMD width.

                                          What should it choose then? I have a Zen 3 processor, and benchmarking some simd I did recently says 32 byte or 64 byte chunks was fastest. But I'm sure I'd get a different result on a different Zen, and different again on Intel's.

                                          How would the library decide what SIMD width I should use?

                                            • Groxx

                                              yesterday at 11:40 PM

                                              It'd need some kind of compile-time hardware-feature-detection, yea? That seems probably feasible since proc macros can do essentially anything they like (worryingly).

                                                • derefr

                                                  yesterday at 11:56 PM

                                                  Only if the end-user is the one compiling the software, on the same very system they'll be running it on. Which is true of GPU shader kernels, due to how GPU drivers work; but isn't generally true of CPU object code (unless you're on Gentoo.)

                                                  What you'd actually want is a matrix of variant implementations burned into the binary, with runtime (or process-boot-time) hardware detection that swaps symbols out to point to the correct variant.

                                                    • adgjlsfhk1

                                                      today at 6:52 AM

                                                      This is one of the nice things about JIT languages. you defer the compiler time decisions to runtime and this get to choose based on what the user has

                                                      • dwattttt

                                                        today at 4:10 AM

                                                        If you want the library to perform that selection, you also need the "correct" / most efficient implementation to be independent of your workload. I'm not that familiar with SIMD performance characteristics, but I wouldn't be surprised if that's not always the case.

                                                          • derefr

                                                            today at 6:19 AM

                                                            From how I understand it, there'd likely only be a single SIMD function impl per uarch that'd actually be fully legally executable without hitting undefined instructions. Plus increasingly-more-generic function impls compiled for lower and lower common-denominator subsets of SIMD functionality. (Ultimately grounding in a non-SIMD impl.)

                                                            If that's the case, then the selection logic would be trivial: figure out the full hierarchical ID of the uarch you're running on, then search for the longest prefix match in the table of available impls.

                                                            If things work more like you're imagining, though, then I suppose the process-boot impl-selector would narrow down the impl matrix to just the subset that are legal on the running uarch; pick one arbitrarily to be active at first; and then wrap the calls in a handler that gradually re-works the called function in a way reminiscent of a profile-guided JIT, but without the need to actually synthesize any code at runtime — instead, it'd just be a multi-armed bandit passing-through-to and re-ranking competitor impls, with decreasing sampling of the non-first-ranked impls as confidence-in-score-separation increases.

                                • grokcodec

                                  yesterday at 10:54 PM

                                  I would love to have an open source Rust SIMD library with the scope and maturity that https://github.com/google/highway brings to C++.

                                    • raphlinus

                                      today at 12:44 AM

                                      This is basically the goal of fearless_simd, but of course achieving the same level of maturity will take time.

                                  • nynx

                                    yesterday at 8:39 PM

                                    Do you have examples of complex algorithms running on the gpu with rust with competative performance? Radix sort might be a good one to start with

                                    • melodyogonna

                                      today at 1:21 AM

                                      Very interesting. But GPU programming gets complicated when you start doing 3d computation on very large data, will be interesting to see how tensor abstraction is built on top of this. Another point is that this is using fixed-width SIMD vectors; unless there is a way to compute this statically based on available GPU info, performance will always be left on the table.

                                      • LegNeato

                                        yesterday at 7:41 PM

                                        Author here, AMA.

                                          • lbhdc

                                            yesterday at 8:08 PM

                                            What is vectorware's business model? Are you planning to sell support/consulting to companies using your stack? Or are you looking to sell licenses to your tool? Or something else?

                                              • LegNeato

                                                yesterday at 8:28 PM

                                                The tentative plan is to open source all the compiler and `std` bits with our products built on top (compilers are not good businesses). More about our products coming in the next couple of months!

                                                  • lbhdc

                                                    yesterday at 9:00 PM

                                                    Looking forward to reading more about it. Good luck on the launch :)

                                            • jcranmer

                                              yesterday at 7:47 PM

                                              The post is kind of vague on the IR you're targeting. Can you give some examples of what the SIMD-ized IR looks like, and how it maps to the target PTX?

                                                • LegNeato

                                                  yesterday at 8:26 PM

                                                  Didn't want to go into crazy detail in the post.

                                                  Each family of operations is a trait parameterized by the operation itself:

                                                    pub trait EvaluateReduction<Operation, T>: LaneEvaluator {
                                                        /// Reduce one distributed definition to an ordinary uniform scalar.
                                                        fn evaluate_reduction(&self, value: LaneValue<Self, role::Distributed, T>) -> T;
                                                    }
                                                  
                                                  
                                                  Call sites name the operation:

                                                    let one   = evaluator.splat::<Splat, _>(1_u32);
                                                    let two   = evaluator.splat::<Splat, _>(2_u32);
                                                    let three = evaluator.binary::<Add, _>(one, two);
                                                  
                                                    let total   = evaluator.reduce::<Sum, u32>(three);   // a uniform u32
                                                    let running = <Executor as EvaluateScan<Scan<Sum, Exclusive>, u32>>::scan(&evaluator, three);
                                                  
                                                  
                                                  Operations like Sum, Max, ReduceXor, Inclusive, and Exclusive are all distinct types.

                                                  As mentioned in the post, execution shape is typed too. A static shuffle takes its control as a type-level constant, and the shuffle mode constrains which controls are expressible:

                                                    // Shift down one lane, keeping our own value where the source is inactive.
                                                    let down  = <Executor as EvaluateShuffle<Shuffle<Down>, DownOrSelf<1>, u32>>::shuffle(&ev, v);
                                                    // Broadcast from lane zero.
                                                    let bcast = <Executor as EvaluateShuffle<Shuffle<Broadcast>, WarpLane<0>, u32>>::shuffle(&ev, down);
                                                    // Butterfly exchange with the neighbor one bit away.
                                                    let bfly  = <Executor as EvaluateShuffle<Shuffle<Xor>, Butterfly<1>, u32>>::shuffle(&ev, bcast);
                                                  
                                                  
                                                  For an example of errors caught, a warp-scoped executor for a device-scoped barrier is a compile error:

                                                    <ScopedWarpExecutor<'_, WarpUniform> as EvaluateBarrier<Barrier<Device>>>::barrier(evaluator)
                                                    // error[E0277]: the trait bound `Device: NvptxBarrierScope` is not satisfied
                                                    //               help: the trait `NvptxBarrierScope` is implemented for `Warp`
                                                  
                                                  
                                                  Strip mining is typed on the amount of work and the lane capacity, and it hands back one chunk at a time along with the predicate saying which lanes live in that chunk:

                                                    // Six work items across four active lanes: two chunks, based at 0 and 4.
                                                    <Executor as EvaluateStripMine<StripMine, (WorkItems, ActiveLanes<StripMined<4>>), i32>>::
                                                        for_each_strip_mined(
                                                            &evaluator,
                                                            (WorkItems::new(6)?, ActiveLanes::new(4)?),
                                                            |index, active| {
                                                             // ...
                                                            },
                                                        );
                                                  
                                                  
                                                  Hopefully that gives the flavor of it.

                                                  • the__alchemist

                                                    yesterday at 7:51 PM

                                                    I'm confused too. How does this fit between these approaches for paraellization:

                                                      - CUDA kernels and Tiles (e.g. Cudarc, cuda-oxide, rust-gpu etc) - SIMD on the GPU. (E.g. as in the title...)
                                                      - CPU SIMD using avx or SSE instructions (And probably thin wrappers for vectors so you can have sane syntax). Or the maybe-upcoming core simd which should abstract over architecture-specific instructions. Magic floats etc which do 4-16 computations at once, but are a bit clumsy to work with
                                                      - Rayon thread pools - arbitrary parallel computations, including SIMD, one per CPU core.
                                                    
                                                    It looks like from the code samples like maybe a cleaner syntax for writing code on the GPU than CUDA kernels? E.g. without mucking with serialization, host and device by abstracting over it? And inspired by core::simd. (Good choice if so, in the interest of standardizing on syntax; I did this for my x86 SIMD vector/quaternion lib as well)

                                                • bbminner

                                                  yesterday at 10:58 PM

                                                  If you have to express your computation using an "array programming DSL" with things like scan and gather anyways - why not opt to use torch/tensorflow/jax or anything else that targets MLIR? An example of writing a relu using an embedded array DSL is really not helping your case either - that's exactly the problem that these other solutions mentioned above are successfully solving for the past ~15y (starting with theano etc). Not sure what this brings to the table - doing that AoT instead of at runtime?

                                                    • LegNeato

                                                      today at 12:12 AM

                                                      The goal of this work is to run existing unmodified CPU libraries (which may use core::simd) on the GPU. If you are manually writing ML-shaped workloads, it doesn't add any value over writing with tech like torch/tensorflow/jax which are custom built for those use-cases (except maybe familiarity if you are a CPU programmer).

                                                  • lbhdc

                                                    yesterday at 8:03 PM

                                                    This is really cool! It sounds like y'all have a compiler fork that you are using to make this work. I wanna tinker with this, is your compiler available?

                                                      • LegNeato

                                                        yesterday at 8:40 PM

                                                        It is not currently available but we intend to make it available after we launch our products.

                                                    • Eridrus

                                                      yesterday at 8:29 PM

                                                      Given the massive demand for GPUs for LLMs, what sorts of work do you expect to economically benefit from utilizing GPUs more?

                                                        • LegNeato

                                                          yesterday at 8:33 PM

                                                          Part of our thesis is that decent GPUs are in every shipping device and most software doesn't use them and should.

                                                            • Eridrus

                                                              yesterday at 8:49 PM

                                                              I guess you're looking at consumer hardware then since servers have exactly what you pay for.

                                                              Can you say more about the application space you're targeting?

                                                      • shay_ker

                                                        yesterday at 10:33 PM

                                                        Hm is the intent to one day replace the CPU?

                                                          • LegNeato

                                                            yesterday at 10:36 PM

                                                            The goal is to use similar abstractions and code across both the CPU and GPU where it makes sense.

                                                        • PoignardAzur

                                                          yesterday at 9:27 PM

                                                          Any thoughts about SIMD-related crates?

                                                          • max-m

                                                            yesterday at 10:48 PM

                                                            How was your day?

                                                            • adityazero

                                                              yesterday at 10:32 PM

                                                              [dead]

                                                              • guess__who

                                                                yesterday at 7:42 PM

                                                                [flagged]

                                                            • frollogaston

                                                              today at 3:38 AM

                                                              I've noticed a lot of articles about SIMD on the HN front page. That's cool, but just wondering, is there some reason this is more in focus lately?

                                                                • vatsachak

                                                                  today at 4:00 AM

                                                                  SIMD is actually underrated still. Programmers should always be thinking about it. It's a free 4x in a lot of cases

                                                                    • pjmlp

                                                                      today at 6:27 AM

                                                                      The main problem with SIMD is it is a complex subject, even if not that good, autovectorization wins over what most common devs know about SIMD.

                                                                      Well now you could in theory AI generate SIMD, which will be vibe coded, as those devs have no idea of its correctness.

                                                                      • frollogaston

                                                                        today at 4:24 AM

                                                                        I did see the article about that too. Don't know about "always" since there are applications like web backends where you're never going to add arrays of floats or something. Even if it's data science stuff, if that's in Python, Numpy is doing the SIMD for you.

                                                                    • skitsofrandom

                                                                      today at 3:58 AM

                                                                      I’m wondering if AI has made SIMD intrinsics much more approachable for many and so there are just more people working on abstractions for their workflow of choice right now. There’s probably a lot of code out there that could benefit from SIMD but the effort to actually use it was too high for the return.

                                                                      • LoganDark

                                                                        today at 3:45 AM

                                                                        Maybe things being on the front page reminds others? After seeing something, sometimes you can have ideas relating to it for a while.

                                                                          • samuell

                                                                            today at 3:52 AM

                                                                            Yes, this kind of thing seems to happen quite often. Popular posts spurring further posts on a theme.

                                                                    • dev_dan_2

                                                                      yesterday at 11:21 PM

                                                                      Really exciting work and great write up, thanks a lot and all the best to your startup!

                                                                      `core` instead of `std` is great too!

                                                                      This will become useful in one of my sideproject where I use bitmaps to speed up pathfinding, exited to try it out!

                                                                      • efnx

                                                                        yesterday at 7:24 PM

                                                                        Congrats to the Rust-GPU folks! Nice to see the good work flowing.

                                                                        • nperez19

                                                                          yesterday at 10:31 PM

                                                                          Love the pendantic mode setting on the website

                                                                            • minraws

                                                                              yesterday at 10:36 PM

                                                                              I don't get what's the value of it not being enabled by default what does the toggle get us, really? Maybe I don't understand web design and it makes it harder to read for some, I am dyslexic and never had any issues.

                                                                                • LegNeato

                                                                                  yesterday at 11:03 PM

                                                                                  It's just a way for us to add minutia and details that most don't care / need to know about. There are three audiences we try to make the posts accessible for: Rust people who don't know about GPUs, GPU people who don't know about Rust, and non-Rust non-GPU people. The toggle lets knowledgable readers go "wait, what about..." and hopefully the toggle answers it.

                                                                                    • minraws

                                                                                      today at 12:04 AM

                                                                                      Does making it the default hurt anyone though? I don't think that 1 subscript adds anything to it..

                                                                                        • LegNeato

                                                                                          today at 12:13 AM

                                                                                          Just distracting / ugly to my eyes.

                                                                              • yesterday at 10:36 PM

                                                                            • the__alchemist

                                                                              yesterday at 8:02 PM

                                                                              Hey - this is probably off-topic/meta, but what is going on with the comments here? Is it bots?

                                                                                • dev_l1x_be

                                                                                  yesterday at 8:07 PM

                                                                                  No idea, but it seems HN needs POW challenges.

                                                                                    • lukan

                                                                                      yesterday at 8:30 PM

                                                                                      Could also just be trolls attracted by the Rust topic.

                                                                                        • dev_l1x_be

                                                                                          yesterday at 9:49 PM

                                                                                          I bet some kid is bored out of his mind and wrote a bot.

                                                                                  • yesterday at 8:08 PM

                                                                                • rust-lang

                                                                                  yesterday at 8:10 PM

                                                                                  [flagged]

                                                                                  • donald-trump

                                                                                    yesterday at 9:16 PM

                                                                                    [flagged]

                                                                                    • donald-trump

                                                                                      yesterday at 9:19 PM

                                                                                      [flagged]

                                                                                      • lx-user

                                                                                        yesterday at 8:07 PM

                                                                                        [flagged]

                                                                                          • yesterday at 8:08 PM

                                                                                        • guess__who

                                                                                          yesterday at 7:42 PM

                                                                                          [flagged]

                                                                                            • LegNeato

                                                                                              yesterday at 7:47 PM

                                                                                              We never mention anything about superiority nor compare with other languages or programming models. This post is about making existing Rust CPU code work on the GPU.

                                                                                                • guess__who

                                                                                                  yesterday at 7:49 PM

                                                                                                  [flagged]

                                                                                                    • fluffybucktsnek

                                                                                                      yesterday at 10:42 PM

                                                                                                      Those aren't lines you are reading. Those are your hallucinations.

                                                                                                      At worst, the post reads like a propaganda for VectorWare, but, overall, it reads more like their insights on the matter.

                                                                                              • kooi

                                                                                                yesterday at 7:56 PM

                                                                                                Useless blabbering.

                                                                                                If you have real feedback, great, but it's useless to rip on the hard work of others without it.

                                                                                                  • fire_wheel

                                                                                                    yesterday at 8:00 PM

                                                                                                    I am rewriting some components in rust - I dont like such sentiment. It negatively impacts the community.

                                                                                                    Rust is better in so many ways.

                                                                                                • throwaway894345

                                                                                                  yesterday at 7:59 PM

                                                                                                  I'm not a Rust user apart from an occasional toy program here and there, but you seem really triggered about a language that other people use. What's the issue?

                                                                                                  • the__alchemist

                                                                                                    yesterday at 7:54 PM

                                                                                                    I care because it means I can use this in a Rust program without a FFI barrier. Regrettably, we have built computing infrastructure as a society with many barriers; programming language is one.

                                                                                                    • extrem-RAM-shor

                                                                                                      yesterday at 8:02 PM

                                                                                                      Rust is the best. No other language is fun enough to program.

                                                                                                  • queisoy

                                                                                                    yesterday at 7:30 PM

                                                                                                    [flagged]