Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm
75 points - last Friday at 11:03 AM
Sourcemschuster91
today at 7:32 PM
> By stacking multiple nanosheet channels, the effective channel width can be maintained even within a highly compact footprint.
The fact that this level of precision can be achieved on 300mm wafers over many dozens of separate steps in separate devices is an insane achievement on its own.
A much greater achievement than training frontier models, or building any kind of software stack, if you ask me.
Yet everybody seems to think the moat is with the AI companies or nvidia.
RicoElectrico
today at 4:32 PM
How about heat? Seems these days it's the heat above everything else that's the issue. And more density would only aggravate it.
Heat is mostly driven by leakage current and gate capacitance.
The big issue today is leakage currents. They typical account for around 30%-50% of total chip thermal budget, and they get increasingly difficult to control with smaller devices and lower voltages. They're also get worse with increased temperature(!).
The stacked devices here aren't the worst for leakage currents, but they're not fantastic either. Look at the 2nd graph in section 5: You'll see that the current never drops to zero over the range of gate-source voltages (for V_DS=0.7V). The minimum point is the best-case leakage current, and you can see it's well above zero! (The units on the vertical axis of the graph are unknown btw: The label reads as "current drain-source, arbitrary units")
What you loose in heat you gain in speed caused by proximity. Perhaps this will allow for lower voltage and thus less heat.
Except hot spots quickly reach the melting point of silicon these days. That creates, let's say, a rather steep drop off in performance.
Pure silicon melts at 1400 C
You must be thinking of something else
kridsdale1
today at 8:18 PM
In NAND, data loss is proportional to temperature. I don’t recall how logic circuit errors behave.
That's always an issue, but the industry seems to be moving away from 2D circuits.
Reducing trace length seems to be the way forward for faster/larger circuits. Signal propagation time on-die is becoming an issue.
Things like Huawei's Logic folding, or TSVs, and so on, attack the issue by reducing signal travel time.
This looks like another building block in that direction.
There's also some push at cooling chips from both sides.
I wonder if the proposed CPU/GPU laser cooling technique that was on here a few days ago would penetrate the Si layers?
https://news.ycombinator.com/item?id=48510375
Not an expert but I wondered this too and did some searching. My understanding is the laser cooling isn't expected to be applicable to silicon logic anytime soon. Its applications are more for specialized contexts like cooling quantum sensors, resonators, imagers, etc.
The big barrier remains heat and this 3D stacking (aka CFET) makes heat worse by increasing density. It's possible much of the density gains offered by CFETs will remain unutilized unless other approaches to solve the fundamental heat problem are found, possibly discovering new high-conductivity MDI materials.
If heat is produced by conductors resistance then shorter paths would lead to less heat produced.
I'm not certain (never did hardware), but I thought the transistor switching cost was one of the bigger sources of energy loss, not internal conductor resistance between transistors?
saltcured
today at 7:10 PM
The shorter connections could lead to faster rise times though, right? I.e. less capacitance or inductance interfering with getting the field gate charged up?
And the main loss with switching transistors is in the intermediate switching states where it has less than its "full" resistance.
Makes sense, I also doubt that they haven't minimized resistance to minimum already.
You're correct. Dynamic power consumption depends heavily on frequency, but it's definitely more of a limiting factor than static power consumption which as I understand it (I'm also not an expert) is mainly important for things like low power microcontrollers.
This seems like it could accelerate the transition to sub-1nm nodes (previously projected to mid 2030s), maybe by the end of this decade.
porridgeraisin
today at 7:12 PM
> A city provides a useful analogy. When available land becomes scarce, urban planners initially reduce the spacing between buildings and use roads and open spaces more efficiently. Eventually, however, further horizontal expansion becomes impractical. At that point, the solution is to build upward. High-rise buildings create more usable space on the same piece of land by utilizing the vertical dimension.
Really? someone tell that to my city
mschuster91
today at 7:33 PM
It only works for cities designed from the ground up for such density, simply because of all the supporting infrastructure that humans need (utilities, roads, public transport, education, entertainment, recreation).
Retrofits are insanely expensive and often fraught with issues.
its_ajseven
last Friday at 11:03 AM
[flagged]