Application / realtime split cores are very common, STM32MP* was designed around the application processor / realtime processor split, I don’t remember if that’s what was on that Beaglebone. Any “big” application processor these days will have a variety of smaller generic cores (Cortex-M style) around it, some which usually handle programmable I/O.
A lot of microcontrollers also have pretty sophisticated interrupt controllers and timing analyzers which can be used to accomplish similar tasks, although they’re usually “programmed” by chaining register effects so it’s nowhere near as elegant as PIO.
Specialized IO coprocessors which are programmed using “code” like PIO is are a little less common, Infineon Peripheral Control Processor springs to mind.
I just refreshed my memory - they were called Programmable Realtime Units on this chip: https://uk.rs-online.com/web/p/microprocessors/1219716
Can the “little” cores in big.little arches be run entirely independently then? That’s pretty cool if so.
> Can the “little” cores in big.little arches be run entirely independently then?
Well, that too :) What I’m referring to is more like Qualcomm “safety island” on Dragonwing, Xilinx RPU, or Allwinner AR100 (I think this is used in 3D printer projects using A64, actually), though - where most modern large “embedded” Linux SoCs have some real time island to talk to the outside world. Cell phone SoCs and stuff like Apple M also have realtime cores hiding in them running blobs, although they’re usually connected to more specific RF or A/V blocks rather than generic IO.
> Specialized IO coprocessors which are programmed using “code” like PIO
Which is exactly what GP was talking about: the TI PRU cores are this.
Yeah, I didn’t realize those were in a Beaglebone ever, I thought it was STM32MPx. So that’s like PIO or PCP more directly.